Yosys — RTL Synthesis for FPGA

Synthesis is the step where a hardware description becomes a real gate network, and until Yosys appeared it was a domain entirely closed to vendors. Yosys reads Verilog, optimises it and produces a netlist; together with nextpnr it enables a complete FPGA workflow for certain devices without a single proprietary tool — from source code to programming file. The licence is permissive (ISC), and it is used both as research infrastructure and in commercial projects. It fits alongside Icarus Verilog and GHDL in this directory.