Digital — The Complete Guide: A Logic Simulator With Export to VHDL and Verilog
Digital is an open-source (GPLv3) logic simulator inspired by Logisim and built for teaching. You assemble a digital circuit on a canvas — gates, flip-flops, counters and memories — and run it step by step or continuously, with the value of every wire on screen.
Digital — logic simulator
Helmut Neemann
Build a logic circuit and watch it run — with export to VHDL and Verilog.
Get it from the vendorWhat you get
- Synthesis from a truth table — enter a table or an expression and get a minimised circuit.
- Circuit analysis — an existing circuit translated back into a truth table.
- Automated tests — test cases saved with the circuit and run in one click.
- Export to VHDL and Verilog — with direct support for several FPGA boards.
- State machines — a simple editor that generates the matching circuit.
How it differs from Logisim
Both suit an introductory logic course. Digital’s advantage is the bridge to practical work: a circuit built in class exports to HDL and can be programmed onto an FPGA, and you can also embed parts written in VHDL or Verilog and run them through GHDL or Icarus Verilog. It is written in Java and runs on every operating system.
Related tools
For the long-established alternative common in courses — Logisim Evolution. For HDL simulation — GHDL and Icarus Verilog.
Logisim-evolution
Logisim-evolution Team
Design and simulate digital logic circuits interactively.
Get it from the vendor
GHDL — VHDL Simulator
GHDL Project
Open-source VHDL compiler and simulator for verifying hardware descriptions before synthesis.
Get it from the vendor
Icarus Verilog
Stephen Williams
A Verilog compiler and simulator for digital design work.
Get it from the vendor
GTKWave
GTKWave Project
A waveform viewer for digital simulation output.
Get it from the vendorThe bottom line
Digital is an excellent teaching tool that takes a student from the first gate to code running on an FPGA. Completely free, commercial use included.