GHDL — The Complete Guide: Open-Source VHDL Simulation, From the Course to the FPGA

GHDL is an open-source compiler and simulator for VHDL. It translates the hardware description into machine code and runs it, so simulation is fast. VHDL is the teaching language in many courses, especially in Europe and in academia, and GHDL is the free way to work with it without an FPGA vendor’s environment.

GHDL — VHDL Simulator

GHDL Project

Open-source VHDL compiler and simulator for verifying hardware descriptions before synthesis.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsSimulation & FEAElectronics Design (EDA)

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What you get

• VHDL standards — support for VHDL-87, 93 and 2008.
• Waveform files — writes VCD and GHW for viewing in GTKWave.
• Automated tests — runs testbenches from the command line, which suits CI pipelines.
• Synthesis — connects to Yosys through a plugin, for an open FPGA flow.
• Framework support — works with open verification frameworks such as VUnit and cocotb.

How to use it

Write the design and its testbench in an editor such as VSCodium, analyse the files, run the simulation and open the waveform file in GTKWave. There is no built-in graphical interface — it is a command-line tool. GHDL is for logical verification; for timing checks on a specific chip you still need the vendor’s tools.

Related tools

To view the waveforms — GTKWave. If you work in Verilog — Icarus Verilog. To draw a circuit and export it to VHDL — Digital.

GTKWave

GTKWave Project

A waveform viewer for digital simulation output.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsSimulation & FEAElectronics Design (EDA)

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Yosys — RTL Synthesis for FPGA

YosysHQ / Claire Wolf

Open-source synthesis tool that turns Verilog into a gate-level netlist, the basis of a fully open FPGA flow.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsElectronics Design (EDA)

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Icarus Verilog

Stephen Williams

A Verilog compiler and simulator for digital design work.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsSimulation & FEAElectronics Design (EDA)

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Digital — logic simulator

Helmut Neemann

Build a logic circuit and watch it run — with export to VHDL and Verilog.

Electrical & ElectronicsSoftware & ComputingCompletely FreeOpen SourceLinuxmacOSWindowsSimulation & FEAElectronics Design (EDA)

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The bottom line

GHDL is the standard free VHDL simulator: fast, stable and available for every operating system, commercial use included.

Further reading

• GTKWave — The Complete Guide: Free Viewing and Analysis of Digital Simulation Waveforms
• Yosys — The Complete Guide: Verilog Synthesis and a Fully Open FPGA Flow
• Icarus Verilog — The Complete Guide: A Small, Simple Verilog Simulator for Courses and Projects