GTKWave — The Complete Guide: Free Viewing and Analysis of Digital Simulation Waveforms

GTKWave is an open-source waveform viewer for digital simulation results. The simulator writes a file with every signal change, and GTKWave displays them on a time axis — like a logic analyser, but on a design that has not been programmed yet.

GTKWave

GTKWave Project

A waveform viewer for digital simulation output.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsSimulation & FEAElectronics Design (EDA)

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What you get

• Formats — VCD, FST, LXT and GHW, from all the common open simulators.
• Hierarchy tree — pick signals by module and drag them into the view.
• Buses — shown in binary, hexadecimal or decimal, or plotted as an analogue trace.
• Markers and measurement — measure the time between events and search for a value or transition.
• Saved layouts — a file with the chosen signals and their order, reopened after every run.

A working tip

For long simulations, save in FST format, which is much smaller and faster than VCD. Keep the layout file in the project, so after each code change you rerun and reopen the same view in one click. GTKWave only displays results — the simulation itself runs in another tool.

Related tools

For Verilog simulation — Icarus Verilog or Verilator. For VHDL simulation — GHDL.

Icarus Verilog

Stephen Williams

A Verilog compiler and simulator for digital design work.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsSimulation & FEAElectronics Design (EDA)

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Verilator

Veripool

Compiles synthesisable Verilog into fast C++ — the quickest free RTL simulator.

Electrical & ElectronicsSoftware & ComputingCompletely FreeOpen SourceLinuxmacOSWindowsSimulation & FEAElectronics Design (EDA)

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GHDL — VHDL Simulator

GHDL Project

Open-source VHDL compiler and simulator for verifying hardware descriptions before synthesis.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsSimulation & FEAElectronics Design (EDA)

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Yosys — RTL Synthesis for FPGA

YosysHQ / Claire Wolf

Open-source synthesis tool that turns Verilog into a gate-level netlist, the basis of a fully open FPGA flow.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsElectronics Design (EDA)

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The bottom line

GTKWave is the window through which you see any open-source digital simulation. Small, stable and completely free.

Further reading

• Icarus Verilog — The Complete Guide: A Small, Simple Verilog Simulator for Courses and Projects
• GHDL — The Complete Guide: Open-Source VHDL Simulation, From the Course to the FPGA
• Verilator — The Complete Guide: The Fastest Free Verilog and SystemVerilog Simulation