Verilator — The Complete Guide: The Fastest Free Verilog and SystemVerilog Simulation

Verilator is not an ordinary simulator but a compiler: it converts synthesisable Verilog and SystemVerilog into a cycle-accurate C++ or SystemC model. You compile and run the model, and it is orders of magnitude faster than event-driven simulators. It is used in real chip and processor projects.

Verilator

Veripool

Compiles synthesisable Verilog into fast C++ — the quickest free RTL simulator.

Electrical & ElectronicsSoftware & ComputingCompletely FreeOpen SourceLinuxmacOSWindowsSimulation & FEAElectronics Design (EDA)

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What you get

• Speed — millions of cycles, for example a processor booting an operating system.
• Linting — strict code checks that catch errors before you even simulate.
• Multithreading — splitting the model across several cores for extra speed.
• Waveform files — VCD and FST for viewing in GTKWave.
• Software integration — testbenches in C++ or in Python (through cocotb), and co-simulation with software models.

What to know

Verilator focuses on synthesisable code and needs a C++ compiler plus some command-line build experience. For an introductory course or a small block, Icarus Verilog is easier to start with. The licence is LGPL or Artistic, and it is free for commercial use too.

Related tools

To synthesise the same code — Yosys. For simple simulation that installs in a minute — Icarus Verilog. If you work in VHDL — GHDL.

Icarus Verilog

Stephen Williams

A Verilog compiler and simulator for digital design work.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsSimulation & FEAElectronics Design (EDA)

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GTKWave

GTKWave Project

A waveform viewer for digital simulation output.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsSimulation & FEAElectronics Design (EDA)

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Yosys — RTL Synthesis for FPGA

YosysHQ / Claire Wolf

Open-source synthesis tool that turns Verilog into a gate-level netlist, the basis of a fully open FPGA flow.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsElectronics Design (EDA)

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GHDL — VHDL Simulator

GHDL Project

Open-source VHDL compiler and simulator for verifying hardware descriptions before synthesis.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsSimulation & FEAElectronics Design (EDA)

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The bottom line

When simulation is too slow or you need many regression runs, Verilator is the fastest free tool available.

Further reading

• Icarus Verilog — The Complete Guide: A Small, Simple Verilog Simulator for Courses and Projects
• GTKWave — The Complete Guide: Free Viewing and Analysis of Digital Simulation Waveforms
• Yosys — The Complete Guide: Verilog Synthesis and a Fully Open FPGA Flow