Yosys — The Complete Guide: Verilog Synthesis and a Fully Open FPGA Flow
Yosys is an open-source synthesis tool: it reads Verilog, optimises it and produces a gate netlist. For years synthesis was a field closed entirely to chip vendors, and Yosys is the foundation of open FPGA flows. The licence is the permissive ISC licence.
Yosys — RTL Synthesis for FPGA
YosysHQ / Claire Wolf
Open-source synthesis tool that turns Verilog into a gate-level netlist, the basis of a fully open FPGA flow.
Get it from the vendorWhat you get
- FPGA synthesis — mapping to the cells of supported families, such as Lattice iCE40 and ECP5.
- A fully open flow — together with nextpnr you place, route and produce a programming file.
- Reports — resource counts, logic cells and memories, early in the design.
- Formal verification — the basis of formal tools that prove properties of a design.
- Scripting — every step is a command, so a repeatable automated flow is easy to build.
What to know
The complete open flow is available only for certain FPGA families; for most AMD and Intel devices you still need the vendor’s environment. Yosys runs from the command line and assumes you know Verilog. VHDL input is possible through a GHDL plugin.
Related tools
For fast simulation of the same code — Verilator or Icarus Verilog. To view waveforms — GTKWave.
Verilator
Veripool
Compiles synthesisable Verilog into fast C++ — the quickest free RTL simulator.
Get it from the vendor
Icarus Verilog
Stephen Williams
A Verilog compiler and simulator for digital design work.
Get it from the vendor
GHDL — VHDL Simulator
GHDL Project
Open-source VHDL compiler and simulator for verifying hardware descriptions before synthesis.
Get it from the vendor
GTKWave
GTKWave Project
A waveform viewer for digital simulation output.
Get it from the vendorThe bottom line
Yosys opened synthesis to everyone. For students, researchers and projects on supported chips, it enables a free and transparent FPGA flow from end to end.