Icarus Verilog — The Complete Guide: A Small, Simple Verilog Simulator for Courses and Projects
Icarus Verilog is an open-source compiler and simulator for the Verilog language. You write a module and a testbench, compile with one command and run — and the result is printed output plus a waveform file. It is small, installs in a minute and is available for every operating system.
Icarus Verilog
Stephen Williams
A Verilog compiler and simulator for digital design work.
Get it from the vendorWhat you get
- Full Verilog for simulation — including non-synthesisable constructs that are handy in testbenches.
- Waveform files — VCD and FST for viewing in GTKWave.
- Some SystemVerilog — support for part of the commonly used language features.
- A simple flow — two commands, compile and run, which is convenient for scripts and automated checks.
- Works with other tools — runs with cocotb for Python testbenches, and is also used inside Digital.
Who it suits
Students in logic design and digital systems courses, and engineers who want to check a small block without installing a heavy FPGA environment. For large designs, such as a complete processor, Verilator is much faster. There is no graphical interface: you work in a text editor and the command line.
Related tools
To view waveforms — GTKWave. For FPGA synthesis — Yosys. If you work in VHDL — GHDL.
GTKWave
GTKWave Project
A waveform viewer for digital simulation output.
Get it from the vendor
Verilator
Veripool
Compiles synthesisable Verilog into fast C++ — the quickest free RTL simulator.
Get it from the vendor
Yosys — RTL Synthesis for FPGA
YosysHQ / Claire Wolf
Open-source synthesis tool that turns Verilog into a gate-level netlist, the basis of a fully open FPGA flow.
Get it from the vendor
GHDL — VHDL Simulator
GHDL Project
Open-source VHDL compiler and simulator for verifying hardware descriptions before synthesis.
Get it from the vendorThe bottom line
Icarus Verilog is the simplest entry point to Verilog simulation — free, light and available everywhere.