OpenROAD — The Complete Guide: Automated Physical Implementation of Digital Chips From RTL to GDSII

OpenROAD is an open toolchain for the physical implementation of digital chips, aiming to go from RTL to a GDSII file with no manual intervention. Together with OpenROAD-flow-scripts it works with open process kits such as SKY130 and GF180, and it is used in research, teaching and projects that have reached real fabrication.

OpenROAD

The OpenROAD Project

An automated RTL-to-GDSII flow for digital chips — floorplanning, placement, clock tree, routing and timing analysis.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxElectronics Design (EDA)

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What you get

• Floorplanning — area planning, pin placement and the power grid.
• Placement — global and detailed placement of standard cells.
• Clock tree — clock tree synthesis.
• Routing — global and detailed.
• Analysis and checks — parasitic extraction, timing analysis and finishing checks.

What you need to start

A Linux environment. You build it from source or run it in Docker. The easiest way in is OpenROAD-flow-scripts with an example design and the SKY130 kit. It is licensed under BSD-3-Clause, commercial use included.

Related tools

For synthesising Verilog into a gate-level netlist — Yosys. For inspecting the resulting GDS file — KLayout. For fast RTL simulation before implementation — Verilator.

Yosys — RTL Synthesis for FPGA

YosysHQ / Claire Wolf

Open-source synthesis tool that turns Verilog into a gate-level netlist, the basis of a fully open FPGA flow.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsElectronics Design (EDA)

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KLayout

Matthias Köfferlein

Viewer and editor for chip mask layouts (GDS2, OASIS) — fast even on huge files, with DRC, LVS and scripting.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSWindowsElectronics Design (EDA)

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Verilator

Veripool

Compiles synthesisable Verilog into fast C++ — the quickest free RTL simulator.

Electrical & ElectronicsSoftware & ComputingCompletely FreeOpen SourceLinuxmacOSWindowsSimulation & FEAElectronics Design (EDA)

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Magic VLSI

Tim Edwards (Open Circuit Design)

A veteran chip layout editor with real-time design-rule checking, parasitic extraction and GDS and LEF/DEF support.

Electrical & ElectronicsCompletely FreeOpen SourceLinuxmacOSElectronics Design (EDA)

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The bottom line

OpenROAD lets students and small teams take a digital chip through the whole flow with open tools — without expensive EDA licences.

Further reading

• Yosys — The Complete Guide: Verilog Synthesis and a Fully Open FPGA Flow
• KLayout — The Complete Guide: Free Viewing and Editing of GDS and OASIS Chip Layouts
• Verilator — The Complete Guide: The Fastest Free Verilog and SystemVerilog Simulation